The present invention relates to a method of and apparatus for processing digital signals, particularly for encoding the digital signals with a frame synchronization code prior to recording and decoding the coded signals upon reproduction.
Various attempts have hitherto been made to achieve high density recording of digitized analog audio signals. One such prior art approach, as shown and described in U.S. Pat. Nos. 3,624,637 and 3,641,525, involves organizing the binary data into a plurality of data segments and translating each data segment to a different bit pattern according to a predetermined rule. IEEE Transactions on Magnetics (Vol. MAG-13, No. 5, September 1977, Page 1202 by G. V. Jacoby) describes a similar technique which is known as Three-Phase Modulation (3PM) system. The coding technique of this type is generally treated in a publication "IBM Journal of Research and Development" (Vol. 14, July 1970, Page 376) by P. A. Franaszek in which Run Length Limited (RLL) coding method is proposed. The RLL coding method involves segmenting binary data into m-bit data segments and translating the m-bit data segments to n-bit codes (where m&lt;n). This method restricts the number of "0" bits in each "0"-bit run length of the n-bit code to a range of from d to k. Because of these parameters the coded signal is described as (m, n, d, k) code.
The method of coding and decoding are currently evaluated in terms of maximum magnetic reversal time (Tmax) which is determined by the maximum run length of "0" bits, minimum magnetic reversal time (Tmin) which is determined by the minimum run length of "0" bits and window time (Tw) needed to detect magnetic reversals. Theoretically, high density recording could be achieved by simply reducing the Tmin value. However, since the recorded signals are reproduced in response to reversals of magnetic poles in the recording medium as a combined waveform of signal components arising from such reversals, the reduction of the Tmin value would result in an appreciable amount of interference between adjacent signal components. Because of this interference, the waveform of the reproduced signals tends to contain erratically occurring peaks and troughs with a resultant variation in amplitude. This leads to the introduction of detection errors.
On the other hand, a reduction of the Tmax value would result in a narrowing of the bandwidth of reproduced signal, causing the clock components to occupy a substantial part of the bandwidth. This allows a simple design for phase locked loop circuits used for regenerating the timing signal. Thus, in order for the phase locked loop to be properly functioning it is desirable that the value of Tmax be as small as possible.
It is desirable that the Tw value be as large as possible since the range for detecting peaks in the reproduced signal and hence the allowance of time-axis deviation of the peak is increased and the instances of detecting false peaks can be decreased.
Various conventional coding systems can be compared with each other in terms of the parameters just described as follows:
______________________________________ Coding Systems Tmin Tmax Tw ______________________________________ FM (Frequency Modulation) 0.5T T 0.5T MFM (Modified FM) T 2T 0.5T M.sup.2 FM (Modified MFM) T 2.5T 0.5T 4/5 GCR (Group Code Recording) 0.8T 2.4T 0.8T 3PM (Three-phase Modulation) 1.5T 6T 0.5T ______________________________________
where, T represents the interbit spacing of the data prior to coding.
The Tmin value of 1.5T is considered to meet the requirement of high density recording. While the 3PM coding meets this requirement, difficulty is encountered when deriving the clock from the train of reproduced binary digits by the use of a phase locked loop.
On the other hand, it is the usual practice to organize a group of successively encoded data segments into a frame by interleaving a frame synchronization code which is used for discrimination during the inverse process of decoding. The current frame sync code has such a bit pattern to ensure against false detection in the presence of jitters.
Although the prior art frame sync code is immune to jitters, it is highly likely that similar bit patterns occur in the information data and false frame sync codes are detected. To avoid this shortcoming, prior art systems are provided with a sync protection circuit which gates on the frame sync by utilizing its periodicity. However, this arrangement is not yet satisfactory because if synchronism is lost it takes long to detect the proper timing and re-synchronize.